IR22771S/IR21771S(PbF) 
13
      www.irf.com
 
 
For this particular PWM scheme another suitable
solution is driving the IR2x771 with a half frequency
SYNC signal (f
SYNC
=f
PWM
/2).
In this case the cut frequency of the input filter is
reduced by half allowing zeroes to be put at f
PWM
 
multiples (i.e. even and odd harmonics cancellation,
no   more   computational   effort   needed   by   the
controller).
Figure 15: Even harmonic cancellation principle 
 
 
 
 
1.6 Input filter gain setting
 
G0 and G1 pins are used to change the time
constant of the integrators of the high side input
filter.
To avoid internal saturation of the input filter, G0
and G1 must be connected according to SYNC
frequency as shown in Table 1. A too small time
constant may saturate the internal integrator, while
a large time constant may reduce accuracy.
G0 and G1 do not affect the overall current sensor
gain.
 
f
PWM
 
G0     G1
> 16 kHz *
V
B
     V
B
 
16 / 10 kHz
V
S
     V
B
 
10 / 6 kHz
V
B
     V
S
 
< 6 kHz
V
S
     V
S
 
 
* 40 kHz
Table 1: G0, G1 gain settings 
 
 
Triangular
Phase voltage
Phase current
Current Mean
Fundamental
harmonic
Fundamental
harmonic
Switching level
Third
harmonic
Third
harmonic
SYNC 1
SYNC 2
Sampling
instant
Sampling
instant
Error
Triangular
Phase voltage
Phase current
Current Mean
Fundamental
harmonic
Fundamental
harmonic
Switching level
Third
harmonic
Stage 1 input:
Input signal
components
(1
st
 and 2
nd
harmonic only)
Third
harmonic
SYNC 1
SYNC 2
Sampling
instant
Sampling
instant
Error
Stage 1
output
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